A comprehensive hardware engineering blueprint detailing the ASIC architecture, memory requirements, and coprocessor interfaces for a next-generation PQC TPM.
Traditional TPM silicon occupies less than 2 mm^2 of silicon area with 16-32 KB of SRAM. Post-quantum lattice cryptography requires substantially larger memory buffers: an ML-KEM-768 operation requires multiple kilobytes of working RAM for polynomial vectors and NTT twiddle factor tables. We examine optimal on-chip SRAM budgeting and area-efficient arithmetic units.
Comparing pure hardwired polynomial multipliers against programmable crypto-engines. Hardwired NTT units achieve orders-of-magnitude faster execution with lower energy consumption, while microcoded RISC-V coprocessors offer cryptographic agility to adapt to future NIST algorithm revisions.
Integrating dual-rail asynchronous logic, randomized clock jitter generators, and top-layer active shield meshes to protect the internal lattice accelerator from microprobing, voltage glitching, and differential power analysis.